If modules are not clearly specified, chip planning relies on netlist partitioning (Chap. 2) to identify such modules in large designs. Assigning shapes and locations to circuit modules during chip planning produces blocks , and enables early estimates of interconnect length, circuit delay, and chip performance.
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Chip planning consists of three major stages: (1) floorplanning (Sects. 3.1 – 3.5 ), (2) pin assignment (Sect. 3.6 ), and (3) power planning (Sect. 3.7 ). Recall from Chap. 2 that a gate-level or RTL netlist can be automatically partitioned into modules. Alternatively, such modules can be extracted from a hierarchical design representation.
The results of partitioning and chip planning greatly affect subsequent design steps and the overall quality of the layout. That is, subsequent design steps (e.g., global and detailed placement and routing) must be performed within the block-level constraints imposed by chip planning.
Large chip modules are laid out as blocks or rectangular shapes on the surface of the chip (Fig. 3.1 ), using the following general steps: Floorplanning determines the locations and dimensions of these shapes, based on the areas and aspect ratios of the modules so as to optimize chip size, reduce wire length, and improve timing.
On-chip supply voltages scale more slowly than chip frequencies and transistor counts. Therefore, currents supplied to the chip steadily increase with each technology generation. Improved packaging and cooling technologies, together with market demands for functionality, lead to ever-greater power budgets and denser power grids.