One way to solve the problem is applying de-tuned harmonic filters or an appropriately sized capacitor to avoid har-monic resonance. Harmonic filters provide the same 60-Hz reactive compensation as capacitors, but they’re typically designed with a parallel resonance point below any expected harmonics on the system.
This resonance can be avoided by putting a detuned reactor in series with the capacitor. The reactor shall be such that the tuning frequency with the capacitor shall be less than the dominant harmonics. This combination of power factor correction capacitor and detuned reactors behaves inductively to frequencies above the tuning frequency.
The traceto the capacitor likewise contributes some inductance and resistance. A real-world capacitor should therefore be modelled as an RLC filter: it has a resonant frequency, above which the effectiveness of the capacitance is can-celled out by the parasitic inductance.
Contrariwise, [Danker 2011] recommends against placing decoupling capacitors in parallel (regard-less of whether these capacitors are different or identical). Finally, [Ott 2009] recommends putting two capacitors in parallel, but in contrast to Archambeault he asserts that both should be identical,1 citing the risk of antiresonance.
It depends on the whole system (containing power planes,decaps etc). When multiple numbers of same value capacitors are used there are high chances of Anti resonance with power planes, same way when multiple numbers of different values capacitors are used there are high chances of anti resonance b/w different capacitor values.
The presence of harmonic distortion due to non-linear loads within the network or due to import of harmonic from grid or power source increases the current flowing through capacitors. This is because the capacitive reactance is inversely proportional to the frequency, consequently subjecting capacitors to overload.